F

FPGA

Hog (HDL-on-git) is a set of Tcl/Shell scripts plus a suitable methodology to handle HDL designs in a git repository. For more information, visit our documentation page: https://cern.ch/hog, or register to our newsletter: http://cern.ch/go/nBn8

A better hardware description language.

The xibif-connection Python package serves as the API to connect to a XiBIF FPGA board.

Éléments liés à mes streams Twitch sur LiteX. Replays sur Twitch (https://www.twitch.tv/lefinnois_) et YT (https://www.youtube.com/@LefStream)

Deterministic timer IP core in VHDL for precise time-based event generation, supporting configurable periods and synchronization mechanisms.

Running legacy Xilinx ISE FPGA software on a MacOS system (including Apple Silicon) using Docker.

Verible build container.

Open source Logic Analyzer based on LiteX SoC

A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector

FreeDev Foundation: Open-source RISC-V hardware for the public good.

EPSILOD is a C11 framework for iterative stencil computations acceleration on heterogeneous and distributed systems, with great scaling capabilities. It is presented as a function which solves a fixed number of iterations of a geometric stencil computation. It also supports device-tailored optimized stencil kernels.

Controllers is a library written in C99 that provides a simplified way to program application that can exploit heterogeneous computational platforms including accelerators and/or multi-core CPUs.

The TrustBird APU development.

The FreeBird APU development.

The compute chiplet, of Kunminghu cores, a shared ARV-Q, and the Ventus GPGPU.

The compute chiplet, of Kunminghu cores and a shared ARV-Q.

The shared code for the I/O chiplet of the FreeDev APUs.

The shared codes for the L3 cache chiplet for the FreeDev APUs.

A minimalist, workstation platform

The FreeNest platform development.