IA-64

Not to be confused with x86-64, AMD's 64-bit extension of x86-32.

IA-64 (Intel Architecture 64 bit) is a RISC, VLIW (very large instruction word) CPU architecture developed jointly by Intel and HP, with the intention of replacing the x86-32, PA-RISC and Alpha CPUs in the server and workstation market first and later in desktops. After many setbacks, the first Itanium CPU, Merced was released in 2001. Due to the delays, disappointing performance and other technical issues, it never obtained the expected popularity, getting itself displaced from the market by AMD's 64-bit extension to x86, x86-64 (also known as AMD64).

The first document describing the new instruction set was published by Intel in May 1999. The name IA-64 was published beforehand, and some of the features were known beforehand (predication and wide-issue were discussed in December 1997 on comp.arch).

In 2019, Intel announced that the latest generation, Kittson, of IA-64 processors would cease production by January 2020, and that shipments would stop in July 2021. With this, Itanium was finally declared obsolete.

Features

• EPIC (Explicitly Parallel Instruction Computing) computing paradigm, moving the responsibility of determining which instructions can be safely executed in parallel to the compiler rather than in the CPU itself (like in any other architecture).
• 128 bit wide instruction bundles, containing 2 or 3 instructions, along with a template (which describes the instruction types and dependency information)
• "register stack engine" which would automatically store some registers to memory on function calls (and load them back on return)
• very large register files, 128 general-purpose integer registers (r0 to r127), 128 floating point registers (f0 to f127), 64 predicate registers (p0 to p63), 8 branch registers (b0 to b7), 128 special-purpose "application registers" and the instruction pointer (ip).
• several features intended to expose out-of-order processing to the compiler
  • explicit loop branches, with rotating registers (for software pipelining)
  • non-faulting loads, "not-a-thing bit" for uninitialized variables
  • loads which check against later stores
• 3 or 4 register, non-destructive format (dest = src1 op src2; dest = src1 * src2 + src3)
• almost all instructions can be predicated (conditionally executed based on the 1-bit predicate registers)
• simple addressing modes (register indirect, with post increment)

A feature initially announced by Intel was native execution of x86 code (including operating systems) for compatibility, but it was removed in the design process due to complexity and low performance.

Implementations

• Merced (released as Itanium, not to be confused with the Itanium Instruction Set aka IA-64)
• McKinley (released as Itanium 2)

Compiler Support

• Open64
• GCC
• LLVM (Very poor support, dropped in 2.6)
• HP's aCC Compiler
• Intel C++ Compiler (Edison Design Group frontend)

External links

• Itanium at Wikipedia
• Itanium at TechPubs