FlyDSL 0.3.2 documentation

FlyDSL is a Python DSL and MLIR compiler stack for authoring high-performance GPU kernels with explicit layout algebra, targeting AMD ROCm/HIP GPUs.

FlyDSL is the Python front-end (Flexible Layout Python DSL) powered by the Fly dialect: an MLIR-native compiler stack with first-class layout IR (!fly.int_tuple, !fly.layout, !fly.coord_tensor, !fly.memref), explicit algebra and coordinate mapping, plus a composable lowering pipeline to GPU/ROCDL.

Getting started

• Install FlyDSL

• Quick start

• API stability

Guides

• Arithmetic types

• Composite types

• Storage and allocator

• Architecture and compilation pipeline

• Layout algebra

• Kernel authoring

• Kernel tuning

• Offline autotune configs

• Prebuilt kernel library

• Testing and benchmarking

• CuTe layout algebra

• External bitcode integration

API reference

• FlyDSL Python DSL

• Compiler and pipeline

• Prebuilt kernels

Tutorials

• Basic usage

• Kernel development